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bit_slice
A. Renee

Registered: 12/12/05
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VLSI Design: Construction of a Pad Frame
#5057691 - 12/13/05 01:56 PM (18 years, 5 months ago) |
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Do any microelectronics or computer hardware type people know anything about construction of the pads for a microprocessor? I have a complete layout for a simple MIPS processor and am now laying out the pad frame. I know that two diodes that are a attached to the circuit have to be configured in such a way to eliminate electrostatic discharge. Has anybody done this before?
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Seuss
Error: divide byzero


Registered: 04/27/01
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Re: VLSI Design: Construction of a Pad Frame [Re: bit_slice]
#5061015 - 12/14/05 04:28 AM (18 years, 5 months ago) |
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Yes, but not for many years. I designed a 32-bit RISC based CPU back in 1994/1995 that I had manufactured using Mosis technology. I was using Mentor Graphics for the design tool. Between the Mosis libraries and mentor graphics, I simply laid out the pad locations. When the software synthesized the die, it used standard pads from the Mosis library, if I remember correctly.
Maxim has some really good tech papers on electrostatic supression. Lemme google and see what I can find. Hmm... not what I was thinking of, but it is a starting place... http://www.maxim-ic.com/appnotes.cfm/appnote_number/639
-------------------- Just another spore in the wind.
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Jim


Registered: 04/07/04
Posts: 20,922
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Re: VLSI Design: Construction of a Pad Frame [Re: Seuss]
#5061020 - 12/14/05 04:32 AM (18 years, 5 months ago) |
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Seuss to the rescue!
I told her there were very educated people that post here, and that someone would know what she was talking about.
-------------------- Use the Fucking Reply To Feature You Lazy Pieces of Shit! afoaf said: Jim, if you were in my city, I would let you fuck my wife.
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bit_slice
A. Renee

Registered: 12/12/05
Posts: 187
Loc: america, fuck yeah
Last seen: 17 years, 1 month
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Re: VLSI Design: Construction of a Pad Frame [Re: Seuss]
#5061163 - 12/14/05 07:19 AM (18 years, 5 months ago) |
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yeah, your project seems very similar. i think adding a couple diodes will take care of it. do you remember doing that?
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Seuss
Error: divide byzero


Registered: 04/27/01
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Re: VLSI Design: Construction of a Pad Frame [Re: bit_slice]
#5061409 - 12/14/05 08:43 AM (18 years, 5 months ago) |
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-------------------- Just another spore in the wind.
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bit_slice
A. Renee

Registered: 12/12/05
Posts: 187
Loc: america, fuck yeah
Last seen: 17 years, 1 month
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Re: VLSI Design: Construction of a Pad Frame [Re: Seuss]
#5061689 - 12/14/05 09:47 AM (18 years, 5 months ago) |
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sweeeet! this is exactly what i need.
you went to Standford???? VERY impressive
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Seuss
Error: divide byzero


Registered: 04/27/01
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Re: VLSI Design: Construction of a Pad Frame [Re: bit_slice]
#5065803 - 12/15/05 04:24 AM (18 years, 5 months ago) |
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> sweeeet! this is exactly what i need.
Cool, glad to help!
> You went to Standford?
Nope, more mid-west, but a very well respected engineering and mining university. I was a comp sci major, but spent more time in the EE labs designing chips and boards than anything else. If you get the chance, design and build your own computer from the transistor level up... it is a very rewarding (and difficult) experience.
I started with the DLX core and pipelined it, added interrupts, faults and traps. I did not try to implement any kind of protected or virtual memory models. It was on par with an old 8088 cpu, but running 32-bits, pipelined, and RISC. This was implemented via Mosis standard cell technology.
I designed a very simple system board, only four layers and all thruhole. Communication was done through an RS232 port driven by a max232 chip. A small EEPROM held a very simple BIOS (I ported the Buffalo OS that Motorolla provides for the HC11). I had a dedicated memory bus and mapped the EEPROM into high memory. I also had a very simple IO bus, though I never bothered to use it for anything.
The entire thing was battery operated and had a built in DC-DC converter to regulate power. I could run on anything from 5v up to 48v and the entire system only drew around 12ma total (at 9v).
I always wanted to add an LCD display and keypad, but never got around to it. Unfortunately, somebody else in the lab decided it was a cool project and stole the board at the end of a semester. He never came back and I didn't notice the theft for a few weeks. (I was in finals mode, not playing in the lab mode.) I didn't have enough money to get the board and cpu manufactured a second time. (It is an expensive project, unless you can get the companies to donate.) I got both the board and CPU donated (around a $4000 donation between the two), but had to pay for all the components... around $300 in parts on the board with all the caps, the dc-dc converter, sockets, and tristate buffers.
-------------------- Just another spore in the wind.
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TheCow
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Re: VLSI Design: Construction of a Pad Frame [Re: Seuss]
#5067953 - 12/15/05 04:21 PM (18 years, 5 months ago) |
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I actually have to build a RISC processor next quarter at my university. But what do you mean from the transistor level up, I mean, did you make NAND or memory chips? Or you mean, you used pre-made MUX's and whatnot, but linked them together. As I mean, sure I know how to make all those chips, but it seems silly and redundant to bother wiring massive amounts of transistors together.
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bit_slice
A. Renee

Registered: 12/12/05
Posts: 187
Loc: america, fuck yeah
Last seen: 17 years, 1 month
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Re: VLSI Design: Construction of a Pad Frame [Re: TheCow]
#5069128 - 12/15/05 09:14 PM (18 years, 5 months ago) |
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just to clarify -- have you already taken VSLI and will be designing the RISC processor in lab next quarter? it would be easier to answer your question if i had a better understanding of your background.
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TheCow
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Re: VLSI Design: Construction of a Pad Frame [Re: bit_slice]
#5069888 - 12/16/05 02:34 AM (18 years, 5 months ago) |
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Oh I was actually talking to Seuss. I know Verilog pretty well Id say, but Ive only taken one class on it.
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Seuss
Error: divide byzero


Registered: 04/27/01
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Re: VLSI Design: Construction of a Pad Frame [Re: TheCow]
#5070034 - 12/16/05 03:47 AM (18 years, 5 months ago) |
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> But what do you mean from the transistor level up
It means that I wrote a book full of VHDL code and used Mentor Graphics to "translate" the VHDL into a network of transistors that will implement the logic defined by the VHDL code. The transistor network definitions were sent too a company and the sent me back a chip. I did not sit there drawing out stick diagrams, nor did I try to define the network of transistors by hand... that would have taken a few million lifetimes to do. I don't see how you could get through a VLSI design class without understanding the basics of the VLSI fabrication process. The classes that I learned this kind of stuff from were all graduate level EE courses. They were considered some of the hardest EE classes at the university and there were usually only two or three of us in the classroom.
-------------------- Just another spore in the wind.
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